Concept of UVM phase

24 Feb 2024

5 mins

We have seen earlier that a modern test bench has lot of components. To achieve a fruitful verification, it is important that all components are in sync with each other. In System Verilog there is no direct mechanism to keep all the components in synchronization and thus, achieving this can be very difficult sometimes. UVM introduced a mechanism to synchronize the components in a more defined way known as phases. In this article we will see the concept of phase in detail without going deep into the implementation.

Introduction

Phases are important to synchronize different components of tb. For example, if driver component starts driving a stimulus whereas monitor is still not built then we might lose sampling some data.

Phases in UVM can be broadly categorized into two groups:

• Non-time-consuming phase – these are the phases which will not consume any time in simulation. This can be related to functions, i.e., the entire code will be executed in the timestep.
• Time consuming phase – these are the phases which can consume time. These can be related to task.

Different Phases

Let us see different phases present in UVM and what are they used for. As mentioned earlier we will focus more on the theory aspect in this article rather than focusing on how to implement them.

Build Phase

This is phase from which UVM simulation starts. This phase does not consume any time. Build phase as the name suggests is used to build all the components. This phase executes in top-down manner which means that the parent components are build first and then child components are built.

Connection phase

This phase is used for connecting TLM ports of a component to another component. This connection later helps in smooth transfer of transactions b/w different components later. This is also a non-time-consuming phase.

This is executed in bottom-up manner, which means that the child components phase is executed first and then the parent components.

End of elaboration phase

This phase comes after connection phase. This marks the end of build phase and indicates all components have been built and connected. This phase is used to display the topology of the built TB. This phase can also be used to fine-tune TB parameters. It is executed in bottom-up manner.

Start of simulation phase

This phase comes just before the actual simulation starts, i.e., before the stimulus is driven from TB. This phase ensures that everything is ready before simulating the DUT and can also be used to fine-tune TB parameters before starting tests. It is executed in bottom-up manner.

Run Phase

Run phase is a time-consuming phase and stimulus is driven in this phase. Thus, the tests are executed in this phase. This is executed parallelly for all the components in different threads like fork join.

It is launched in parallel with other run time phases, such as reset_phase, configure_phase, main_phase, and shutdown_phase. These sub-phases can be used to perform specific tasks related to the DUT or the interface, such as generating a reset, configuring the registers, driving the main stimulus, or shutting down the test.

Phase objection

Run phase is a time-consuming phase and different components can consume different time. UVM provides an objection mechanism by which a component which is taking longer time to complete task can create an objection. This prevents other components move from run to extract phase.

For example, comp A is taking 40ns to complete a task and comp B is taking 100ns to complete tasks. Both comp A and B will raise objection in time 0ns. At 40ns comp A will drop objection as it has completed its task. But as there is still one objection from comp B, comp A will stay in run phase until the objection is dropped by comp B at 100ns.

It is important to raise objection in run phase if consume time in run phase, otherwise simulation would immediately move to extract phase at 0ns without consuming any time. UVM moves to another phase when there is no objection and thus raising objections correctly is important.

We will see this in more detail once we start implementing components. For now, familiarity with objection concept will help in understanding phases better.

Extract Phase

Extract phase is a non-time-consuming phase and is executed once all the stimulus is over. In this phase, we extract data which will be analysed by the end-of-sim scoreboards.

Check Phase

Once all the data has been extracted, end of sim scoreboard will evaluate the data and check if the dut behaviour was correct or not. This is done in check phase. Check phase is also non-time consuming.

Report Phase

Report phase is used to print the results from the checkers/scoreboard and prints the summaries of test objective. This phase is also non-time-consuming phase.

Final phase

Final phase is the last phase before simulation ends and it can be used for last minute cleanups. Also, used to complete any other outstanding actions that the testbench has not already completed. It is executed in top-down manner.

Conclusion

UVM phases are a powerful mechanism to control the execution flow of the testbench components and to synchronize them across the simulation. By understanding the purpose and the order of each phase, verification engineers can create efficient and reusable testbenches that follow the UVM methodology.

Summary of phases

Below table summarizes different phases of UVM in terms of time consumed and execution manner.

This article was focused on theoretical aspects so that readers are aware of the basic concepts before we start the actual implementation. In next articles we will how UVM topology works and learn more about the UVM in-built classes.